1. Field of the Invention
The present invention relates to a hybrid integrated circuit device in which a power metal oxide semiconductor field effect transistor (MOS-FET) is mounted in a bare chip state.
2. Description of the Related Art
FIG. 4 is an exploded perspective view showing an example of a power control unit mounted on, for example, a vehicle and accommodating the above-described type of hybrid integrated circuit device in a package thereof. In the hybrid integrated circuit device, power MOS-FETs 2 used for controlling power, control ICs 1 and so on are mounted on a circuit substrate 3 with a circuit pattern 3a printed on the surface thereof. The power MOS-FETs 2 are mounted in a bare chip state. External connection terminals 10 through 15 extend from the circuit substrate 3 for electrical connection with an external device. The circuit substrate 3 with the components mounted thereon is accommodated in a package body 100a of a package 100. The package has a lid 100b. The external connection terminals 10 through 15 are exposed from the package 100.
FIG. 5 schematically illustrates the configuration of a conventional hybrid integrated circuit device. In the figure, reference numeral 1 denotes a control IC. Reference numeral 2 denotes a power MOS-FET. Reference numeral 3 denotes a circuit substrate. Reference numeral 4 denotes a control voltage supply line which is part of the circuit pattern 3a shown in FIG. 4. Reference symbol R1 is a resistor inserted in the control voltage supply line 4 between the control IC 1 and a gate terminal of the power MOS-FET 2. Reference numeral R2 denotes a resistor connected between the gate terminal of the power MOS-FET 2 and a source terminal thereof. Reference numerals 10 through 15 denote external connection terminals extending from the circuit substrate 3.
The operation of the conventional hybrid integrated circuit device will be described below. The control IC 1 applies a control voltage to the gate terminal of the power MOS-FET 2 via the control voltage supply line 4 according to the control signal input from the external connection terminals 12 and 13. Current flow between the drain and source of the power MOS-FET 2 is turned on and off by that control voltage applied to the gate terminal. The control voltage applied between the gate and source of the power MOS-FET 2 at that time is about 10 volts for general transistors. About 5 volts are applied in the case of low-voltage driven transistors. Alternatively, a voltage waveform signal whose pulse width is controlled is applied.
When the power MOS-FET is mounted in a bare chip state in the hybrid integrated circuit device arranged in the manner described above, the damage during the manufacturing process of the hybrid integrated circuit device, the stress due to an external stress or latent defects caused by the manufacturing process or the structure of a power MOS-FET device must be eliminated initially, and a burn-in screening test is, then, conducted on the power MOS-FET. This burn-in screening test may be conducted before the assembly on preliminary processed products. Alternatively, the test may be conducted during the assembly of the device or after the assembly thereof by simulating a normal operation (a burn-in test which uses a normal voltage). However, it is difficult to actually perform the burn-in test because connection of the terminals is not yet completed at the processing stage of the device or because the circuit connection must be temporarily disconnected by any means so that a burn-in test voltage can be directly .applied to the gate terminal of the power MOS-FET. In an effective burn-in test which can be conducted in a short period of time, a voltage higher than that normally applied to the gate terminal of the power MOS-FET is applied. However, in the conventional hybrid integrated circuit device, this adversely affects other components and cannot be used.